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| issue 1.7 1/48 ? stpc client pc compatible embedded microprocessor february 8, 2000 figure 1. logic diagram ? powerful x86 processor ? 64-bit 66mhz bus interface ? 64-bit dram controller ? svga graphics controller ? uma architecture ? video scaler ? video output port ? video input port ? crt controller ? 135mhz ramdac ? 2 or 3 line flicker filter ? scan converter ? pci master / slave / arbiter ? isa master/slave ? ide controller ? dma controller ? interrupt controller ? timer / counters ? power management stpc client overview the stpc client integrates a standard 5th generation x86 core, a dram controller, a graphics subsystem, a video pipeline, and support logic including pci, isa, and ide controllers to provide a single consumer orientated pc compatible subsystem on a single device. the device is based on a tightly coupled unified memory architecture (uma), sharing the same memory array between the cpu main memory and the graphics and video frame buffers. extra facilities are implemented to handle video streams. features include smooth scaling and colour space conversion of the video input stream and mixing of the video stream with non-video data from the frame buffer. the chip also includes anti-flicker filters to provide a stable, high-quality digital tv output. the stpc client is packaged in a 388 plastic ball grid array (pbga). pbga388 x86 core host i/f dram vip pci pci bus isa eid pci isa bus crt hw monitor tv output sync output col- col- our vid- ccir input eide 2d anti- ipc
stpc client 2/48 issue 1.7 - february 8, 2000 ? x86 processor core ? fully static 32-bit 5-stage pipeline, x86 proc- essor with dos, windows and unix compat- ibility. ? can access up to 4gb of external memory. ? kbytes unified instruction and data cache with write back and write through capability. ? parallel processing integral floating point unit, with automatic power down. ? clock core speeds up to of 75 mhz. ? fully static design for dynamic clock control. ? low power and system management modes. ? optimized design for 3.3v operation. ? dram controller ? integrated system memory and graphic frame memory. ? supports up to 128 mbytes system memory in 4 banks and as little as mbytes. ? supports 4mbytes, 8mbites, 16mbites, 32mbites single-sided and double-sided dram simms. ? four quad-word write buffers for cpu to dram and pci to dram cycles. ? four 4-word read buffers for pci masters. ? supports fast page mode & edo drams. ? programmable timing for dram parameters including cas pulse width, cas pre-charge time, and ras to cas delay. ? 60, 70, 80 & 100ns dram speeds. ? memory hole size of 1 mbyte to 8 mbytes supported for pci/isa buses. ? hidden refresh. to check if your memory device is supported by the stpc, please refer to table 7-69 in the programming manual. ? graphics controller ? 64-bit windows accelerator. ? backward compatibility to svga standards. ? hardware acceleration for text, bitblts, trans- parent blts and fills. ? up to 64 x 64 bit graphics hardware cursor. ? up to 4mb long linear frame buffer. ? 8-, 16-, and 24-bit pixels. ? crt controller ? integrated 135mhz triple ramdac allowing up to 1024 x 768 x 75hz display. ? 8-, 16-, 24-bit per pixels. ? interlaced or non-interlaced output. ? video pipeline ? two-tap interpolative horizontal filter. ? two-tap interpolative vertical filter. ? colour space conversion (rgb to yuv and yuv to rgb). ? programmable window size. ? chroma and colour keying allowing video overlay. ? programmable two tap filter with gamma cor- rection or three tap flicker filter. ? progressive to interlaced scan converter. ? video input port ? decodes video inputs in itu-r 601/656 com- patible formats. ? optional 2:1 decimator ? stores captured video in off setting area of the onboard frame buffer. ? video pass through to the onboard pal/ ntsc encoder for full screen video images. ? hsync and b/t generation or lock onto external video timing source. ? pci controller ? integrated pci arbitration interface able to directly manage up to 3 pci masters at a time. ? translation of pci cycles to isa bus. ? translation of isa master initiated cycle to pci. ? support for burst read/write from pci master. ? the pci clock runs at a third or half cpu clock speed. stpc client issue 1.7 - february 8, 2000 3/48 ? isa master/slave ? the isa clock generated from either 14.318mhz oscillator clock or pci clock ? supports programmable extra wait state for isa cycles ? supports i/o recovery time for back to back i/ o cycles. ? fast gate a20 and fast reset. ? supports the single rom that c, d, or e. blocks shares with f block bios rom. ? supports flash rom. ? buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. ? ide interface ? supports pio ? supports up to mode 5 timings ? supports up to 4 ide devices ? individual drive timing for all four ide devices ? concurrent channel operation (pio modes) - 4 x 32-bit buffer fifo per channel ? support for pio mode 3 & 4 ? support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. ? supports both legacy & native ide modes ? supports hard drives larger than 528mb ? support for cd-rom and tape peripherals ? backward compatibility with ide (ata-1). ? integrated peripheral controller ? 2x8237/at compatible 7-channel dma con- troller. ? 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. ? three 8254 compatible timer/counters. ? power management ? four power saving modes: on, doze, stand- by, suspend. ? programmable system activity detector ? supports smm. ? supports stopclk. ? supports io trap & restart. ? independent peripheral time-out timer to monitor hard disk, serial & parallel ports. ? supports rtc, interrupts and dmas wake-up stpc client 4/48 issue 1.7 - february 8, 2000 update history for overview issue 1.7 - february 8, 2000 5/48 update history for overview the following changes have been made to the board layout chapter on 02/02/2000. the following changes have been made to the board layout chapter from revision 1.0 to release 1.2. section change text added to check if your memory device is supported by the stpc, please refer to table 7-69 host address to ma bus mappingin the programming manual. section change text n/a replaced afully pc compatibleo with awith dos, windows and unix compatibilityo n/a replaced a133 mhz o with 75 mhzo n/a removed adrivers for windows and other operating systems.o n/a removed a requires external frequency synthesizer and reference sources.o n/a replaced a chroma and colour keying for integrated video overlay .o with achroma and colour keying allowing video overlay. n/a replaced aaccepts video inputs in ccir 601/656 or itu-r 601/656, and decodes the stream .o with a decodes video inputs in itu-r 601/ 656 compatible formats . n/a replaced afully compliant with pci 2.1 specification. integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters.o with aintegrated pci arbitration interface able to directly manage up to 3 pci masters at a time.o n/a replaced a0.33x and 0.5x cpu clock pci clock.o with athe pci clock runs at a third or half cpu clock speed.o n/a removed asupports flash rom.o n/a replaced asupports isa hidden refresh.o with asupports flash rom.o n/a replaced a buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant.o with abuffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. a n/a replaced a supports pio and bus master ideo with asupports pioo n/a removed atransfer rates to 22 mbytes/seco n/a added aindividual drive timing for all four ide devices a n/a replaced aconcurrent channel operation (pio & dma modes) - 4 x 32-bit buffer fifo per channelo with aconcurrent channel operation (pio modes) - 4 x 32-bit buffer fifo per channelo n/a removed asupport for dma mode 1 & 2.o asupport for 11.1/16.6 mb/s, i/o channel ready pio data transfers.o asupports 13.3/16.6 mb/s dma data transferso abus master with scatter/gather capability a amulti-word dma support for fast ide drives a aindividual drive timing for all four ide devices a asupports both legacy & native ide modeso asupports hard drives larger than 528mbo asupport for cd-rom and tape peripheralso abackward compatibility with ide (ata-1).o adrivers for windows and other oseso update history for overview 6/48 issue 1.7 - february 8, 2000 n/a added asupport for 11.1/16.6 mb/s, i/o channel ready pio data transfers.o asupports both legacy & native ide modeso asupports hard drives larger than 528mbo asupport for cd-rom and tape peripheralso abackward compatibility with ide (ata-1).o n/a removed aco-processor error support logic.o n/a replaced asupports smm and apmo with asupports smmo n/a removed aslow system clock down to 8mhzo aslow host clock down to 8hzo aslow graphic clock down to 8hzo section change text general description issue 1.7 - february 8, 2000 7/48 1.general description at the heart of the stpc client is an advanced processor block, dubbed the st x86. the st x86 includes a powerful x86 processor core along with a 64-bit dram controller, advanced 64bit acceler- ated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt controller, dma con- troller, interval timer and isa bus) and eide con- troller. the stpc client has in addition to the 5st86 a video subsystem and high quality digital televi- sion output. the stmicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. the core has all the functionality of the st microelectronics standard x86 processor products, including the low power system management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while run- ning in isolated smm address space, the smm in- terrupt routine can execute without interfering with the operating system or application programs. further power management facilities include a suspend mode that can be initiated from either hardware or software. because of the static nature of the core, no internal data is lost. the stpc client makes use of a tightly coupled unified memory architecture (uma), where the same memory array is used for cpu main memo- ry and graphics frame-buffer. this significantly re- duces total system memory with system perform- ances equal to that of a comparable solution with separate frame buffer and system memory. in ad- dition, memory bandwidth is improved by attach- ing the graphics engine directly to the 64-bit proc- essor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the sys- tem with 320mb/s peak bandwidth, double that of an equivalent system using 32 bits. this allows for higher screen resolutions and greater colour depth. the processor bus runs at the speed of the processor (dx devices) or half the speed (dx2 de- vices). the `standard' pc chipset functions (dma, inter- rupt controller, timers, power management logic) are integrated with the x86 processor core. the pci bus is the main data communication link to the stpc client chip. the stpc client trans- lates appropriate host bus i/o and memory cycles onto the pci bus. it also supports the generation of configuration cycles on the pci bus. the stpc client, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci mandatory header regis- ters in type 0 pci configuration space for easy porting of pci aware system bios. the device contains a pci arbitration function for three exter- nal pci devices. the stpc client integrates an isa bus controller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc client chip set through this bus. an industry standard eide (ata 2) controller is built into the stpc client and connected internally via the pci bus. graphics functions are controlled by the on-chip svga controller and the monitor display is man- aged by the 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations, which include hard- ware acceleration of text, bitblts, transparent blts and fills. these operations can operate on off- screen or on-screen areas. the frame buffer size is up to 4 mbytes anywhere in the physical main memory. the graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate above display resolution. stpc client provides several additional functions to handle mpeg or similar video streams. the video input port accepts an encoded digital video stream in one of a number of industry standard formats, decodes it, optionally decimates it by a factor of 2:1, and deposits it into an off screen area of the frame buffer. an interrupt request can be generated when an entire field or frame has been captured. the video output pipeline incorporates a video- scaler and colour space converter function and provisions in the crt controller to display a video window. while repainting the screen the crt con- troller fetches both the video as well as the normal non-video frame buffer in two separate internal fifos (256-bytes each). the video stream can be colour-space converted (optionally) and smooth general description 8/48 issue 1.7 - february 8, 2000 scaled. smooth interpolative scaling in both hori- zontal and vertical direction are implemented. col- our and chroma key functions are also imple- mented to allow mixing video stream with non-vid- eo frame buffer. the video output passes directly to the ramdac for monitor output or through another optional col- our space converter (rgb to 4:2:2 ycrcb) to the programmable anti-flicker filter. the flicker filter is configured as either a two line filter with gamma correction (primarily designed for dos type text) or a 3 line flicker filter (primarily designed for win- dows type displays). the flicker filter is optional and can be software disabled for use with large screen area's of video. the video output pipeline of the stpc client in- terfaces directly to the external digital tv encoder (stv0119). it takes a 24 bit rgb non-interlaced pixel stream and converts to a multiplexed 4:2:2 ycrcb 8 bit output stream, the logic includes a progressive to interlaced scan converter and logic to insert appropriate ccir656 timing reference codes into the output stream. it facilitates the high quality display of vga or full screen video streams received via the video input port to standard ntsc or pal televisions. the stpc client core is compliant with the ad- vanced power management (apm) specification to provide a standard method by which the bios can control the power used by personal comput- ers. the power management unit module (pmu) controls the power consumption by providing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agency's energy star computer program. the pmu pro- vides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand- by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system per- formance in various power down states of the sys- tem including full power on state. - power control outputs to disable power from dif- ferent planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi in- terrupts to cpu so that the smm software can put the system in decreasing states of power con- sumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and sus- pend mode. these correspond to decreasing lev- els of power savings. power down puts the stpc client into suspend mode. the processor completes execution of the current instruction, any pending decoded instruc- tions and associated bus cycles. during the sus- pend mode, internal clocks are stopped. remov- ing power down, the processor resumes instruc- tion fetching and begins execution in the instruc- tion stream at the point it had stopped. a reference design for the stpc client is availa- ble including the schematics and layout files, the design is a pc atx motherboard design. the de- sign is available as a demonstration board for ap- plication and system development. the stpc client is supported by several bios vendors, including the super i/o device used in the reference design. drivers for 2d accelerator, video features and eide are available on various operating systems. the stpc client has been designed using mod- ern reusable modular design techniques, it is pos- sible to add to or remove the standard features of the stpc client or other variants of the 5st86 family. contact your local stmicroelectonics sales office for further information. general description issue 1.7 - february 8, 2000 9/48 figure 1-1. functional description. x86 core host i/f dram 2d svga vip pci m/s pci bus crtc hw cursor monitor tv output sync output anti-flicker colour space colour key chroma video pipeline ccir input isa eide pci m/s isa bus ipc eide general description 10/48 issue 1.7 - february 8, 2000 figure 1-2. pictorial block diagram typical application stpc client isa pci 4x 16-bit edo drams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy monitor tv stv0119 video svga ccir601 ccir656 s-vhs rgb pal ntsc irq dma.req dma.ack dmux dmux mux mux rtc pin description issue 1.7 - february 8, 2000 11/48 2.pin description 2.1. introduction the stpc client integrates most of the functional- ities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devices are totally assimilated to the stpc client. this offers improved performance due to the tight coupling of the processor core and its peripherals. as a result many of the external pin connections are made di- rectly to the on-chip peripheral functions. figure 2-1 shows the stpc client's external inter- faces. it defines the main busses and their func- tion. table 2-1 describes the physical implementa- tion listing signals type and their functionality. ta- ble 2-2 provides a full pin listing and description of the pins. table 2-3 provides a full listing of pin lo- cations of the stpc client package by physical connection. please refer to the pin allocation drawing for reference. note: several interface pins are multiplexed with other functions, refer to the pin description sec- tion for further details table 2-1. signal description group name qty basic clocks reset & xtal (sys) 14 memory interface (dram) 89 pci interface (excluding vdd5) 54 isa / ide / ipc combined interface 83 video input (vip) 9 tv output (tv) 10 vga monitor interface (vga) 10 grounds 69 v dd 26 analog specific v cc /v dd 14 reserved/test/ misc./ speaker 10 total pin count 388 figure 2-1. stpc client external interfaces south north pci x86 dram vga vip tv sys isa/ide ipc 89 10 9 10 54 14 73 10 stpc client pin description 12/48 issue 1.7 - february 8, 2000 table 2-2. definition of signal pins signal name dir description qty basic clocks resets & xtal sysrsti# i system reset / power good 1 sysrsto#* o reset output to system 1 xtali i 14.3mhz external oscillator input 1 xtalo i/o 14.3mhz external oscillator input 1 pci_clki i 33mhz pci input clock 1 pci_clko o 33mhz pci output clock (from internal pll) 1 isa_clk o isa clock output - multiplexer select line for ipc 1 isa_clk2x o isa clock x 2 output - multiplexer select line for ipc 1 osc14m* o isa bus synchronisation clock 1 hclk* o host clock (test) 1 dev_clk o 24mhz peripheral clock (floppy drive) 1 gclk2x* i/o 80mhz graphics clock 1 dclk* i/o 135mhz dot clock 1 dclk _dir* i dot clock direction 1 v dd _xxx_pll power supply for pll clocks memory interface ma[11:0]* i/o memory address 12 ras#[3:0] o row address strobe 4 cas#[7:0] o column address strobe 8 mwe# o write enable 1 md[63:0]* i/o memory data 64 pci interface ad[31:0]* i/o pci address / data 32 cbe[3:0]* i/o bus commands / byte enables 4 frame#* i/o cycle frame 1 trdy#* i/o target ready 1 irdy#* i/o initiator ready 1 stop#* i/o stop transaction 1 devsel#* i/o device select 1 par* i/o parity signal transactions 1 serr#* o system error 1 lock# i pci lock 1 pci_req#[2:0]* i pci request 3 pci_gnt#[2:0]* o pci grant 3 pci_int[3:0]* i pci interrupt request 4 vdd5 i 5v power supply for pci esd protection 4 isa and ide combined address/data la[23:22]*/ scs3#,scs1# i/o unlatched address (isa) / secondary chip select (ide) 2 la[21:20]*/ pcs3#,pcs1# i/o unlatched address (isa) / primary chip select (ide) 2 la[19:17]*/ da[2:0] o unlatched address (isa) / address (ide) 3 rmrtccs#* / dd[15] i/o rom/rtc chip select / data bus bit 15 (ide) 1 kbcs#* / dd[14] i/o keyboard chip select / data bus bit 14 (ide) 1 note; * denotes theat the pin is v 5t (see section 4. ) pin description issue 1.7 - february 8, 2000 13/48 rtcrw#* / dd[13] i/o rtc read/write / data bus bit 13 (ide) 1 rtcds#* / dd[12] i/o rtc data strobe / data bus bit 12 (ide) 1 sa[19:8]* / dd[11:0] i/o latched address (isa) / data bus (ide) 16 sa[7:0] i/o latched address (ide) 4 sd[15:0]* i/o data bus (isa) 16 isa/ide combined control iochrdy* / diordy i/o i/o channel ready (isa) - busy/ready (ide) 1 isa control ale* o address latch enable 1 bhe#* i/o system bus high enable 1 memr#*, memw#* i/o memory read and memory write 2 smemr#*, smemw#* o system memory read and memory write 2 ior#*, iow#* i/o i/o read and write 2 master#* i add on card owns bus 1 mcs16#*, iocs16#* i memory/io chip select16 2 ref#* o refresh cycle. 1 aen* o address enable 1 iochck#* i i/o channel check. 1 isaoe#* o bidirectional oe control 1 gpiocs#* i/o general purpose chip select 1 ide control pirq* i primary interrupt request 1 sirq* i secondary interrupt request 1 pdrq* i primary dma request 1 sdrq* i secondary dma request 1 pdack#* o primary dma acknowledge 1 sdack#* o secondary dma acknowledge 1 pior#* i/o primary i/o read 1 piow#* o primary i/o write 1 sior#* i/o secondary i/o read 1 siow#* o secondary i/o write 1 ipc irq_mux[3:0]* i multiplexed interrupt request 4 dreq_mux[1:0]* i multiplexed dma request 2 dack_enc[2:0]* o dma acknowledge 3 tc* o isa terminal count 1 monitor interface red, green, blue o red, green, blue 3 vsync* o vertical synchronization 1 hsync* o horizontal synchronization 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 scl / ddc[1]* i/o i c interface - clock / can be used for vga ddc[1] signal 1 table 2-2. definition of signal pins signal name dir description qty note; * denotes theat the pin is v 5t (see section 4. ) pin description 14/48 issue 1.7 - february 8, 2000 sda / ddc[0]* i/o i c interface - data / can be used for vga ddc[0] signal 1 video input vclk* i pixel clock 1 vin[7:0]* i yuv video data input ccir 601 or 656 8 digital tv output tv_yuv[7:0]* o digital video outputs 8 odd_even* o frame synchronisation 1 vcs* o horizontal line synchronisation 1 miscellaneous st[6:0] i/o test/misc. pins 7 clkdel[2:0]* i/o reserved (test/misc pins) 3 table 2-2. definition of signal pins signal name dir description qty note; * denotes theat the pin is v 5t (see section 4. ) pin description issue 1.7 - february 8, 2000 15/48 2.2.signal descriptions 2.2.1. basic clocks resets & xtal pwgd system reset/power good. this input is low when the reset switch is depressed. other- wise, it reflects the power supply's power good signal. pwgd is asynchronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of pwgd. xtali 14.3mhz pull down (10 k w ) xtalo 14.3mhz external oscillator input these pins are the 14.318 mhz external oscillator input; this clock is used as the reference clock for the in- ternal frequency synthesizer to generate the hclk, clk24m, gclk2x and dclk clocks. hclk host clock. this is the host 1x clock. its frequency can vary from 25 to 75 mhz. all host transactions and pci transactions are synchro- nized to this clock. this clock drives the dram controller to execute the host transactions. in nor- mal mode, this output clock is generated by the in- ternal pll. gclk2x 80mhz graphics clock. this is the graphics 2x clock, which drives the graphics en- gine and the dram controller to execute the graphics and display cycles. normally gclk2x is generated by the internal fre- quency synthesizer, and this pin is an output. by setting a bit in strap register 2, this pin can be made an input so that an external clock can re- place the internal frequency synthesizer. dclk 135mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can go from 8mhz (using internal pll) up to 135 mhz, and it is required to have a worst case duty cycle of 60-40. dclk_dir dot clock direction. specifies if dclk is an input (0) or an output (1). dev_clk 24mhz peripheral clock output. this 24mhz signal is provided as a convenience for the system integration of a floppy disk driver func- tion in an external chip. 2.2.2. memory interface ma[11:0] memory address output. these 12 mul- tiplexed memory address pins support external dram with up to 4k refresh. these include all 16m x n and some 4m x n dram modules. the address signals must be externally buffered to support more than 16 dram chips. the timing of these signals can be adjusted by software to match the timings of most dram modules. md[63:0] memory data i/o. this is the 64-bit memory data bus. if only half of a bank is populat- ed, md63-32 is pulled high, data is on md31-0. md[40-0] are read by the device strap option reg- isters during rising edge of pwgd. ras#[3:0] row address strobe output. there are 4 active low row address strobe outputs, one for each bank of the memory. each bank contains 4 or 8-bytes of data. the memory controller allows half of a bank (4 bytes) to be populated to enable memory upgrade at finer granularity. the ras# signals drive the simms directly with- out any external buffering. these pins are always outputs, but they can also simultaneously be in- puts, to allow the memory controller to monitor the value of the ras# signals at the pins. cas#[7:0] column address strobe output. there are 8 active low column address strobe outputs, one for each byte of the memory. the cas# signals drive the simms either directly or through external buffers. these pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the cas# signals at the pins. mwe# write enable output. write enable speci- fies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write ena- ble controls all drams. it can be externally buff- ered to boost the maximum number of loads (dram chips) supported. the mwe# signals drive the simms directly with- out any external buffering. 2.2.3. video input vclk pixel clock input. vin[7:0] yuv video data input ccir 601 or 656. time multiplexed 4:2:2 luminance and chromi- nance data as defined in itu-r rec601-2 and rec656 (except for ttl input levels). this bus in- terfaces with an mpeg video decoder output port and typically carries a stream of cb, y, cr, y digit- al video at vclk frequency, clocked on the rising edge (by default) of vclk. a 54-mbit/s `double' cb, y, cr, y input multiplex is supported for double encoding applications (rising and falling edge of ckref are operating). 2.2.4. tv output tv_yuv[7:0] digital video outputs. pin description 16/48 issue 1.7 - february 8, 2000 odd_even frame synchronization . vcs horizontal line synchronization . 2.2.5. pci interface pci_clki 33mhz pci input clock this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33mhz pci output clock. this is the master pci bus clock output. ad[31:0] pci address/data. this is the 32-bit pci multiplexed address and data bus. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transac- tions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc client owns the bus and outputs when the stpc client owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc client owns the pci bus. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc client is the target of the current bus transaction. it is used as an input when stpc cli- ent initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc client initiates a bus cycle on the pci bus. it is used as an input during the pci cycles targeted to the stpc client to determine when the current pci master is ready to complete the cur- rent transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc client and is used as an output when a pci master cycle is targeted to the stpc client. devsel# i/o device select. this signal is used as an input when the stpc client initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output ei- ther when the stpc client is the target of the cur- rent pci transaction or when no other device as- serts devsel# prior to the subtractive decode phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if the target aborts an stpc client initiated pci transaction. its assertion by either the stpc client or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pci_req#[2:0] pci request. these pins are the three external pci master request pins. they indi- cate to the pci arbiter that the external agents re- quire use of the bus. pci_gnt#[2:0] pci grant. these pins indicate that the pci bus has been granted master, re- questing it on its pci_req#. 2.2.6. isa/ide combined address/data la[23]/scs3# unlatched address (isa) / sec- ondary chip select (ide). this pin has two func- tions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 23 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high secondary slave ide chip select signal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. pin description issue 1.7 - february 8, 2000 17/48 la[22]/scs1# unlatched address (isa) / sec- ondary chip select (ide) this pin has two func- tions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pin is isa bus un- latched address bit 22 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pin is in input mode. when the ide bus is active, this signal is used as the active high secondary slave ide chip select signal. this signal is to be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[21]/pcs3# unlatched address (isa) / primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pin is isa bus un- latched address bit 21 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pin is in input mode. when the ide bus is active, this signas is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[20]/pcs1# unlatched address (isa) / primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pin is isa bus un- latched address bit 20 for 16-bit devices. when the isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pin is in input mode. when the ide bus is active, this signals is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[19:17]/da[2:0] unlatched address (isa) / ad- dress (ide). these pins are multi-function pins. they are used as the isa bus unlatched address bits [19:17] for isa bus or the three address bits for the ide bus devices. when used by the isa bus, these pins are isa bus unlatched address bits 19-17 on 16-bit devices. when the isa bus is accessed by any cycle initiat- ed from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. for ide devices, these signals are used as the da[2:0] and are connected directly or through a buffer to da[2:0] of the ide devices. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored before being con- nected to the ide devices. sa[19:8]/dd[11:0] unlatched address (isa) / data bus (ide). these are multifunction pins. when the isa bus is active, they are used as the isa bus system address bits 19-8. when the ide bus is active, they serve as ide signals dd[11:0]. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. ide devices are connected to sa[19:8] directly and the isa bus is connected to these pins through two ls245 transceivers. the transceiver oes are connected to isaoe # and the dir is con- nected to master # . the transceiver bus signals are connected to the cpc and ide dd busses and b bus signals are connected to isa sa bus. dd[15:12] databus (ide). the high 4 bits of the ide databus are combined with several of the x- bus lines. refer to the following section for x-bus pins for further information. sa[7:0] isa bus address bits [7:0]. these are the 8 low bits of the system address bus of isa on 8- bit slot. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these pins are the external databus to the isa bus. 2.2.7. isa/ide combined control iochrdy/diordy channel ready (isa) / busy / ready (ide). this is a multi-function pin. when the isa bus is active, this pin is iochrdy. when the ide bus is active, this serves as ide signal di- ordy. iochrdy is the i/o channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc client. the stpc client monitors this signal as an input when per- forming an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc client since the access to the system memory can be consid- erably delayed due to crt refresh or a write back cycle. pin description 18/48 issue 1.7 - february 8, 2000 2.2.8. isa control sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. isa_clk isa clock output (also multiplexer se- lect line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexor control lines for the interrupt controller interrupt input lines. this is a divided down version of either the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal at twice the frequency of the clock signal for the isa bus. it is also used with isa_clk as the multiplex- or control lines for the interrupt controller interrupt input lines. osc14m isa bus synchronization clock output. this is the buffered 14.318 mhz clock to the isa bus. ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc client to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or isa master cycles by the stpc client. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc cli- ent generates smemr# signal of the isa bus only when the address is below 1mbyte or the cycle is a refresh cycle. smemw# system memory write. the stpc cli- ent generates smemw# signal of the isa bus only when the address is below 1mbyte. ior# i/o read. this is the i/o read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the i/o write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select 16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc client ignores this signal during i/o and refresh cycles. iocs16# i/o chip select 16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc client does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc client is exe- cuted as an extended 8-bit i/o cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc client performs a refresh cycle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a re- fresh cycle. the stpc client performs a pseudo hidden re- fresh. it requests the host bus for two host clocks to drive the refresh address and capture it in exter- nal buffers. the host bus is then relinquished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to i/o devices to ignore the ior#/iow# signal during dma transfers. iochck# i/o channel check. i/o channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. pin description issue 1.7 - february 8, 2000 19/48 isaoe# bidirectional oe control. this signal con- trols the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select 1. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be used by the pmu unit to control the external peripheral devices to power down or any other desired function. this pin is also serves as a strap input during re- set. 2.2.9. ide control pirq primary interrupt request. interrupt request from primary ide channel. sirq secondary interrupt request. interrupt re- quest from secondary ide channel. pdrq primary dma request. dma request from primary ide channel. sdrq secondary dma request. dma request from secondary ide channel. pdack# primary dma acknowledge. dma ac- knowledge to primary ide channel. sdack# secondary dma acknowledge. dma acknowledge to secondary ide channel. pior# primary i/o read. primary channel read. active low output. piow# primary i/o write . primary channel write. active low output. sior# secondary i/o read . secondary channel read. active low output. siow# secondary i/o write. secondary channel write. active low output. 2.2.10. x-bus interface pins / ide data rmrtccs# / dd[15] rom/real time clock chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as rm- rtccs#. this signal is asserted if a rom access is decoded during a memory cycle. it should be combined with memr# or memw# signals to properly access the rom. during an i/o cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior#+ or iow# signals to properly access the real time clock. when isaoe# is inactive, this signal is used as ide dd[15] signal. this signal must be ored externally with isaoe# and is then connected to rom and rtc. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor. kbcs# / dd[14] keyboard chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as kbcs#. this signal is assert- ed if a keyboard access is decoded during a i/o cycle. when isaoe# is inactive, this signal is used as ide dd[14] signal. this signal must be ored externally with isaoe# and is then connected to the keyboard. an ls244 or equivalent function can be used if oe# is con- nected to isaoe# and the output is provided with a weak pull-up resistor. rtcrw# / dd[13] real time clock rw. this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is as- serted for any i/o write to port 71h. when isaoe# is inactive, this signal is used as ide dd[13] signal. this signal must be ored externally with isaoe# and then connected to the rtc. an ls244 or equivalent function can be used if oe# is connect- ed to isaoe# and the output is provided with a weak pull-up resistor. rtcds# / dd[12] real time clock ds . this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcds. this signal is asserted for any i/o read to port 71h. when isaoe# is inactive, this signal is used as ide dd[12] signal. this signal must be ored externally with isaoe# and is then connected to rtc. an ls244 or equiv- alent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor. 2.2.11. ipc irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc cli- ent using isaclk and isaclkx2 as the input se- lection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq pin of the rtc. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be en- coded before connection to the stpc client using pin description 20/48 issue 1.7 - february 8, 2000 isaclk and isaclkx2 as the input selection strobes. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc client using isaclk and isaclkx2 as the input selection strobes. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc client before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. 2.2.12. monitor interface red, green, blue rgb video outputs. these are the 3 analog color outputs from the ramdacs vsync vertical synchronization pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronization pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. an external voltage reference is connected to this pin to bias the dac. rset resistor current set. this reference cur- rent input to the ramdac is used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally con- nected to v dd through pull-up resistors. they can instead be used for accessing i c devic- es on board. ddc1 and ddc0 correspond to scl and sda respectively. 2.2.13. miscellaneous st[6], reserved. st[5] this is used for speaker output. st[4] reserved. st[3:0] the pins are for testing the stpc. the default settings on these pins should be 1111 for the stpc to function correctly. by setting the st[3:0] to 0111, the stpc is tristated. clkdel[2:0] reserved . the pins are reserved for test and miscellaneous functions) pin description issue 1.7 - february 8, 2000 21/48 table 2-3. pinout. pin # pin name af3 pwgd af15 xtali ae16 xtalo g23 hclk f25 dev_clk ac5 gclk2x ad5 dclk af5 dclk_dir ad15 ma[0] af16 ma[1] ac15 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ac17 ma[6] ae18 ma[7] ad17 ma[8] af18 ma[9] ae19 ma[10] af19 ma[11] ad18 ras#[0] ae20 ras#[1] ac19 ras#[2] af20 ras#[3] ae21 cas#[0] ac20 cas#[1] af21 cas#[2] ad20 cas#[3] ae22 cas#[4] af22 cas#[5] ad21 cas#[6] ae23 cas#[7] ac22 mwe# af23 md[0] ae24 md[1] af24 md[2] ad25 md[3] ac25 md[4] ac26 md[5] ab24 md[6] aa25 md[7] aa24 md[8] y25 md[9] y24 md[10] v23 md[11] w24 md[12] v26 md[13] v24 md[14] u23 md[15] u24 md[16] r26 md[17] p25 md[18] p26 md[19] n25 md[20] n26 md[21] m25 md[22] m26 md[23] m24 md[24] m23 md[25] l24 md[26] j25 md[27] j26 md[28] h26 md[29] g25 md[30] g26 md[31] ad22 md[32] ad23 md[33] ae26 md[34] ad26 md[35] ac24 md[36] ab25 md[37] ab26 md[38] y23 md[39] aa26 md[40] y26 md[41] w25 md[42] w26 md[43] v25 md[44] u25 md[45] u26 md[46] t25 md[47] r25 md[48] t24 md[49] r23 md[50] r24 md[51] n23 md[52] p24 md[53] n24 md[54] l25 md[55] l26 md[56] k25 md[57] k26 md[58] k24 md[59] h25 md[60] j24 md[61] h23 md[62] h24 md[63] pin # pin name f24 pci_clki d25 pci_clko a20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] d15 ad[16] a14 ad[17] c15 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] c13 ad[23] a12 ad[24] b11 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par d7 serr# a6 lock# c21 pci_req#[0] a21 pci_req#[1] b20 pci_req#[2] pin # pin name pin description 22/48 issue 1.7 - february 8, 2000 c22 pci_gnt#[0] b21 pci_gnt#[1] d20 pci_gnt#[2] d24 pci_int[0] c26 pci_int[1] a25 pci_int[2] b24 pci_int[3] f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g3 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8]/dd[0] l2 sa[9]/dd[1] k3 sa[10]/dd[2] l1 sa[11]/dd[3] m2 sa[12] / dd[4] m1 sa[13] / dd[5] l3 sa[14] / dd[6] n2 sa[15] / dd[7] m4 sa[16] / dd[8] n1 sa[17] / dd[9] m3 sa[18] / dd[10] p4 sa[19] / dd[11] p3 rtcds / dd[12] r2 rtcrw# / dd[13] n3 kbcs# / dd[14] p1 rmrtccs# / dd[15] r1 sd[0] t2 sd[1] r3 sd[2] t1 sd[3] r4 sd[4] u2 sd[5] t3 sd[6] u1 sd[7] u4 sd[8] v2 sd[9] pin # pin name u3 sd[10] v1 sd[11] w2 sd[12] w1 sd[13] v3 sd[14] y2 sd[15] ae4 sysrsto# ad4 isa_clk ae5 isa_clk2x c6 osc14m w3 ale aa2 bhe# y4 memr# aa1 memw# y3 smemr# ab2 smemw# aa3 ior# ac2 iow# ab4 master# ac1 mcs16# ab3 iocs16# ad2 ref# ac3 aen ad1 iochck# af2 isaoe# ae3 gpiocs# y1 iochrdy b1 pirq c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pior# e4 piow# e3 sior# e1 siow# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] a23 dack_enc[1] b22 dack_enc[2] d22 tc pin # pin name ae6 red ad6 green af6 blue ae9 vsync af9 hsync ad7 vref_dac ae8 rset ac9 comp af8 ddc[1] / scl ad8 ddc[0] / sda ad14 vclk ae13 vin[0] ac12 vin[1] ad12 vin[2] ae14 vin[3] ac14 vin[4] af14 vin[5] ad13 vin[6] ae15 vin[7] af10 vtv_yuv[0] ac10 vtv_yuv[1] ae11 vtv_yuv[2] ad10 vtv_yuv[3] af11 vtv_yuv[4] ae12 vtv_yuv[5] af12 vtv_yuv[6] ad11 vtv_yuv[7] ae10 vcs ad9 odd_even b4 st[0] d5 st[1] a4 st[2] c5 st[3] b3 st[4] c4 st[5] a3 st[6] c7 clkdel[0] b5 clkdel[1] a5 clkdel[2] ac7 vdd_dac1 af4 vdd_dac2 w4 vdd_gclk_pll ab1 vdd_dclk_pll f26 vdd_hclk_pll g24 vdd_devclk_pll pin # pin name pin description issue 1.7 - february 8, 2000 23/48 a16 vdd5 b12 vdd5 b9 vdd5 d18 vdd5 a22 vdd b14 vdd c9 vdd d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd g1 vdd k23 vdd l4 vdd l23 vdd p2 vdd t4 vdd t23 vdd t26 vdd aa4 vdd aa23 vdd ab23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd ad19 vdd af13 vdd ae7 vss_dac1 af7 vss_dac2 e25 vss_dll e26 vss_dll a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss pin # pin name m11:16 vss n4 vss n11:16 vss p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1:2 vss ae25 vss af1 vss af25 vss af26 vss pin # pin name pin description 24/48 issue 1.7 - february 8, 2000 update history for pin description chapter issue 1.7 - february 8, 2000 25/48 2.3 update history for pin description chapter the following changes have been made to the pin description chapter on 08/02/2000 the following changes have been made to the pin description chapter on 13/01/2000 dclk dot clock / pixel clock. this clock supplies the display controller, the video pipeline, the ramdac, and the tv output logic. its value is dependent on the selected display mode. its frequency can be as high as 135 mhz. this signal is either driven by the internal pll to a minimum of 8mhz or by an external oscillator. the direction can be controlled by a strap option or an internal register bit. the following changes have been made to the pin description chapter on 28/09/99 the following changes have been made to the pin description chapter on 23/09/99 the following changes have been made to the pin description chapter on 11/08/99 removed statement; athe direction can be controlled by a strap option or an internal register bit.o section change text 2.2.3. replaced signals video_d[7:0] with vin, vtv_bt# with odd_even, vtv_synch with vcs. section change text 2.2. added a to a minimum of 8mhzo section change text table 2-1. changed updated signal pin counts and added abbreviations to table. figure 2-1. changed updated external interface pin count table 2-2. replaced apwgdo with asysrsti#o 2.2.1. moved pci_clki and pci_clko moved from 2.2.1. to 2.2.5. 2.2.1. moved isa_clk and isa_clkx2 moved from 2.2.1. to 2.2.8. 2.2.3. replaced avideo interfaceo with avideo inputo section change text 2.2.13. added anote; by setting signals st[3:0] to the following value allows the stpc to be put tristate. this means the stpc is switched off and no signals are being driven.a update history for pin description chapter 26/48 issue 1.7 - february 8, 2000 the following changes have been made to the pin description chapter from revision 1.0 to release 1.2. section change text 2.1. replaced ainternalo with aassimilated a 2.2.1. replaced athe dram controller to execute the host transactions is also driven by this clocko with athis clock drives the dram controller to execute the host transactionso 2.2.1. replaced aad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions.o with aad[31:0] pci address/data. this is the 32-bit pci multiplexed address and data bus. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions.o 2.2.6. replaced aide devices are connected to sa[19:8] directly and isa bus is connected to these pins through two ls245 transceivers. the oe of the transceivers are connected to isaoe # and the dir is connected to master # . the a bus sig- nals of the transceivers are connected to cpc and ide dd bus and the b bus signals are connected to isa sa bus.o with aide devices are connected to sa[19:8] directly and the isa bus is connected to these pins through two ls245 transceivers. the transceiver oes are con- nected to isaoe # and the dir is connected to master # . the transceiver bus signals are connected to the cpc and ide dd busses and b bus signals are connected to isa sa bus.o 2.2.6. replaced afor ide devices, these signals are used as the da[2:0] and are connected to da[2:0] of ide devices directly or through a buffer. if the toggling of signals is to be masked during isa bus cycles, they can be externally ored before being connected to the ide devices.o with afor ide devices, these signals are used as the da[2:0] and are connected di- rectly or through a buffer to da[2:0] of the ide devices. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored before being connected to the ide devices.o 2.2.8. replaced aiocs16# io chip select16. this signal is the decode of the isa bus sa15-0 address pins of without any qualification of the command signals. the stpc client does not drive iocs16# (similar to pc-at design). an isa master ac- cess to an internal register of the stpc client is executed as an extended 8-bit io cycle.o with aiocs16# io chip select16. this signal is the decode of sa15-0 address pins of the isa address bus without any qualification of the command signals. the stpc client does not drive iocs16# (similar to pc-at design). an isa master access to an internal register of the stpc client is executed as an extended 8- bit io cycle.o 2.2.12. added athey can instead be used for accessing i c devices on board. ddc1 and ddc0 correspond to scl and sda respectively.o 2.2.12. replaced updated table 3 strap option issue 1.7 - february 8, 2000 27/48 3. strap option this chapter defines the stpc client strap op- tions and their location memory data lines refer to designation location actual settings set to '0' set to '1' md0 - reserved - - - - md1 - reserved - - - - md2 dram bank 1 speed index 4a, bit 2 user defined 70 ns 60 ns md3 speed index 4a, bit 3 pull up - - md4 type index 4a, bit 4 user defined edo fpm md5 dram bank 0 speed index 4a, bit 5 user defined 70 ns 60 ns md6 speed index 4a, bit 6 pull up md7 type index 4a, bit 7 user defined edo fpm md8 - reserved index 4b, bit 0 pull up - - md9 - reserved index 4b, bit 1 - - - md10 dram bank 3 speed index 4b, bit 2 user defined 70 ns 60 ns md11 speed index 4b, bit 3 pull up - - md12 type index 4b, bit 4 user defined edo fpm md13 dram bank 2 speed index 4b, bit 5 user defined 70 ns 60 ns md14 speed index 4b, bit 6 pull up md15 type index 4b, bit 7 user defined edo fpm md16 - reserved index 4c, bit 0 pull up - - md17 pci clock pci_clko divisor index 4c, bit 1 user defined hclk /2 hclk /3 md18 - reserved index 4c, bit 2- pull up - - md19 - reserved index 4c, bit 3 pull up - - md20 - reserved index 4c, bit 4 pull up - - md21 - reserved index 5f, bit 0 pull up - - md22 - reserved index 5f, bit 1 pull up - - md23 - reserved index 5f, bit 2 pull up - - md24 hclk hclk pll speed index 5f, bit 3 user defined 000 reserved md25 index 5f, bit 4 user defined 001 reserved md26 index 5f, bit 5 user defined 010 reserved user defined 011 25 mhz user defined 100 50 mhz user defined 101 60 mhz user defined 110 66 mhz user defined 111 75 mhz md27 - reserved - pull up - - md28 - reserved - pull up - - md29 - reserved - pull up - - md30 - reserved - pull up - - md31 - reserved - pull down - - md32 - reserved - pull up - - md33 - reserved - pull up - - md34 - reserved - pull down - - md35 - reserved - pull up - - md36 - reserved - - - - md37 - reserved - - - - strap option 28/48 issue 1.7 - february 8, 2000 note; setting of strap options md [15:2] have no effect on the dram controller but are purely meant for software issues. i.e. readable in a reg- ister. 3.1 power on strap registers description 3.1.1 strap register 0 index 4ah (strap0) bits 7-0; this register reflect the status of pins md[7:0] respectively. they are expected to be connected on the system board to the simm con- figuration pins as follows: note that the simm speed and type information read here is meant only for the software and is not used by the hardware. the software must pro- gram the host and graphics dram controller con- figuration registers appropriately based on these bits. this register defaults to the values sampled on md[7:0] pins after reset. 3.1.2 strap register 1 index 4bh (strap1) bits 7-0; this register reflect the status of pins md[15:8] respectively. they are expected to be connected on the system board to the simm con- figuration pins as follows: note that the simm speed and type information read here is meant only for the software and is not used by the hardware. the software must pro- gram the host and graphics dram controller con- figuration registers appropriately based on these bits. this register defaults to the values sampled on md[15:8] pins after reset. 3.1.3 strap register 2 index 4ch (strap2) bits 4-0; this register reflect the status of pins md[20:16] respectively.they are use by the chip as follows: bit 4-2; reserved. bit 1; this bit reflects the value sampled on md[17] pin and controls the pci clock output as follows: 0: pci clock output = hclk / 2 1: pci clock output = hclk / 3. bit 0; reserved. this register defaults to the values sampled on md[20:16] pins after reset. md38 - reserved - - - - md39 - reserved - - - - md40 - reserved - - - - md41 - reserved - - - - md42 - reserved - - - - md43 - reserved - - - - memory data lines refer to designation location actual settings set to '0' set to '1' bit sampled description bit 7 simm 0 dram type bits 6-5 simm 0 speed bit 4 simm 1 dram type: bits 3-2 simm 1 speed bit 1 reserved bit 0 reserved bit sampled description bit 7 simm 2 dram type bits 6-5 simm 2 speed bit 4 simm 3 dram type bits 3-2 simm 3 speed bit 1 reserved bit 0 reserved strap option issue 1.7 - february 8, 2000 29/48 3.1.4 hclk pll strap register index 5fh (hclk_strap) bits 5-0 of this register reflect the status of the md[26:21] & are used as follows: bit 5-3 these pins reflect the value sampled on md[26:24] pins respectively and control the host clock frequency synthesizer bit 2- 0 reserved this register defaults to the values sampled on above pins after reset. these pin must not be pulled low for normal sys- tem operation. strap registers [43:27] are reserved. electrical specifications 30/48 issue 1.7 - february 8, 2000 4. electrical specifications 4.1 introduction the electrical specifications in this chapter are val- id for the stpc client. 4.2 electrical connections 4.2.1 power/ground connections/ decoupling due to the high frequency of operation of the stpc client, it is necessary to install and test this device using standard high frequency techniques. the high clock frequencies used in the stpc cli- ent and its output buffer circuits can cause tran- sient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 4.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 kw ( 10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 kw ( 10%) pull-up resistor to pre- vent spurious operation. 4.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 4.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc client device. stresses be- yond those listed under table 4-1 limits may cause permanent damage to the device. these are stress ratings only and do not imply that oper- ation under any conditions other than those spec- ified in section ooperating conditionso. exposure to conditions beyond table 4-1 may (1) reduce device reliability and (2) result in prema- ture failure even when there is no immediately ap- parent sign of failure. prolonged exposure to con- ditions at or near the absolute maximum ratings (table 4-1) may also result in reduced useful life and reliability. note 1 : -40 c limit of t case (extended temperature range) is given a s a preliminary specification and so as all the -40 c related data. table 4-1. absolute maximum ratings symbol parameter minimum maximum units v ddx dc supply voltage -0.3 4.0 v v i ,v o digital input and output voltage -0.3 vdd + 0.3 v v 5t 5volt tolerance 2.5 5 v v esd esd capacity (human body mode) 1500 v t stg storage temperature -40 +150 c t case operating case temperature (note 1) -40 +100 c p tot total power dissipation 4.8 w electrical specifications issue 1.7 - february 8, 2000 31/48 4.4 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not 100% tested. 3. detail of pins refer to section 2.2. 4.5 ac characteristics table 4-4 through table 4-8 list the ac character- istics including output delays, input setup require- ments, input hold requirements and output float delays. these measurements are based on the measurement points identified in figure 4-1 and figure 4-2. the rising clock edge reference level vref , and other reference levels are shown in table 4-3 below for the stpc client. input or out- put signals must cross these levels during testing. figure 4-1 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 4-1. table 4-2. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, tcase = 0 to 100 c (commercial range) or -40 to 100 c (industrial range) unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v v dd5 5v operating voltage note 3 4.5 5 5.5 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w h clk internal clock (note 1) 75 mhz v ref dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 4-3. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v electrical specifications 32/48 issue 1.7 - february 8, 2000 figure 4-1 drive level and measurement points for switching characteristics figure 4-2 clk timing measurement points clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1 electrical specifications issue 1.7 - february 8, 2000 33/48 table 4-4. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 13 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 12 ns t4 pci_clki to par valid 2 12 ns t5 pci_clki to trdy# valid 2 13 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 14 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 14 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 3 ns t12 pci_req#[2:0] setup to pci_clki 10 ns t13 pci_req#[2:0] hold from pci_clki 1 ns t14 cbe#[3:0] setup to pci_clki 7 ns t15 cbe#[3:0] hold to pci_clki 5 ns t16 irdy# setup to pci_clki 7 ns t17 irdy# hold to pci_clki 4 ns t18 frame# setup to pci_clki 7 ns t19 frame# hold from pci_clki 3 ns table 4-5. dram bus ac timing name parameter min max unit t22 hclk to ras#[3:0] valid 17 ns t23 hclk to cas#[7:0] bus valid 17 ns t24 hclk to ma[11:0] bus valid 17 ns t25 hclk to mwe# valid 17 ns t26 hclk to md[63:0] bus valid 25 ns t27 md[63:0] generic setup 7 ns t28 gclk2x to ras#[3:0] valid 17 ns t29 gclk2x to cas#[7:0] valid 17 ns t30 gclk2x to ma[11:0] bus valid 17 ns t31 gclk2x to mwe# valid 17 ns t32 gclk2x to md[63:0] bus valid 23 ns t33 md[63:0] generic hold 0 ns electrical specifications 34/48 issue 1.7 - february 8, 2000 table 4-6. video input/tv output ac timing name parameter min max unit t34 dclk to tv_yuv[7:0] bus valid 18 ns t35 vin[7:0] setup to vclk 5 ns t36 vin[7:0] hold from vclk 3 ns t37 vclk to odd_even valid 21 ns t38 vclk to vcs valid 21 ns t39 odd_even setup to vclk 10 ns t40 odd_even hold from vclk 5 ns t41 vcs setup to vclk 10 ns t42 vcs hold from vclk 5 ns table 4-7. graphics adapter (vga) ac timing name parameter min max unit t43 dclk to vsync valid 45 ns t44 dclk to hsync valid 45 ns table 4-8. isa bus ac timing name parameter min max unit t45 xtalo to la[23:17] bus active 60 ns t46 xtalo to sa[19:0] bus active 60 ns t47 xtalo to bhe# valid 62 ns t48 xtalo to sd[15:0] bus active 35 ns t49 pci_clki to isaoe# valid 28 ns t50 xtalo to gpiocs# valid 60 ns t51 xtalo to ale valid 62 ns t52 xtalo to memw# valid 50 ns t53 xtalo to memr# valid 50 ns t54 xtalo to smemw# valid 50 ns t55 xtalo to smemr# valid 50 ns t56 xtalo to ior# valid 50 ns t57 xtalo to iow# valid 50 ns mechanical data issue 1.7 - february 8, 2000 35/48 5. mechanical data 5.1 388-pin package dimension the pin numbering for the stpc 388-pin plastic bga package is shown in figure 5-1. dimensions are shown in figure 5-2, table 5-1 and figure 5-3, table 5-2. figure 5-1. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 11 13 15 17 19 21 23 25 2468101214161820222426 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 1113151719212325 2468101214161820222426 mechanical data 36/48 issue 1.7 - february 8, 2000 figure 5-2. 388-pin pbga package - pcb dimensions table 5-1. 388-pin pbga package - pcb dimensions symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail a1 ball pad corner d f e g c mechanical data issue 1.7 - february 8, 2000 37/48 figure 5-3. 388-pin pbga package - dimensions table 5-2. 388-pin pbga package - dimensions symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g mechanical data 38/48 issue 1.7 - february 8, 2000 5.2 388-pin package thermal data 388-pin pbga package has a power dissipation capability of 4.5w which increases to 6w when used with a heatsink. structure in shown in figure 5-4. thermal dissipation options are illustrated in fig- ure 5-5 and figure 5-6. figure 5-4. 388-pin pbga structure thermal balls power & ground layers signal layers figure 5-5. thermal dissipation without heatsink ambient board case junction board ambient ambient case junction board rca rjc rjb rba 66 125 8.5 rja = 13 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls mechanical data issue 1.7 - february 8, 2000 39/48 figure 5-6. thermal dissipation with heatsink board ambient case junction board ambient ambient case junction board rca rjc rjb rba 36 50 8.5 rja = 9.5 c/w airflow = 0 board dimensions: the pbga is centered on board copper thickness: -17 m m for internal layers -34 m m for external layers - 10.2 cm x 12.7 cm - 4 layers (2 for signals, 1 gnd, 1vcc) there are no other devices heat sink is 11.1 c/w 1 via pad per ground ball (8-mil wire) 40% copper on signal layers board temperature taken at the center balls mechanical data 40/48 issue 1.7 - february 8, 2000 board layout issue 1.7 - february 8, 2000 41/48 6. board layout 6.1 thermal dissipation thermal dissipation of the stpc depends mainly on supply voltage. as a result, when the system does not need to work at 3.3v, it may be to reduce the voltage to 3.15v for example. this may save few 100's of mw. the second area that can be concidered is un- used interfaces and functions. depending on the application, some input signals can be grounded, and some blocks not powered or shutdown. clock speed dynamic adjustment is also a solution that can be used along with the integrated power man- agement unit. the standard way to route thermal balls to internal ground layer implements only one via pad for each ball pad, connected using a 8-mil wire. with such configuration the plastic bga 388 pack- age dissipates 90% of the heat through the ground balls, and especially the central thermal balls which are directly connected to the die, the re- maining 10% is dissipated through the case. add- ing a heat sink reduces this value to 85%. as a result, some basic rules have to be applied when routing the stpc in order to avoid thermal problems. first of all, the whole ground layer acts as a heat sink and ground balls must be directly connected to it as illustrated in figure 6-1. if one ground layer is not enough, a second ground plane may be added on the solder side. figure 6-1. ground routing pad for ground ball thru hole to ground layer t o pl a y e r : s i g n a l s g r o u n dl a y e r p o w e r l a y e r b o t t o m l a y e r : s i g n a l s + l o c a l g r o u n d l a y e r ( i f n e e d e d ) note: for better visibility, ground balls are not all routed. board layout 42/48 issue 1.7 - february 8, 2000 when considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. a 1-wire connection is shown in figure 6-2. the use of a 8-mil wire results in a thermal resistance of 105 c/w assuming copper is used (418 w/ m. k). this high value is due to the thickness (34 m m) of the copper on the external side of the pcb. considering only the central matrix of 36 thermal balls and one via for each ball, the global thermal resistance is 2.9 c/w. this can be easily im- proved by using four 10 mil wires to connect to the four vias around the ground pad link as in figure 6-3. this gives a total of 49 vias and a global resis- tance for the 36 thermal balls of 0.6 c/w. the use of a ground plane like in figure 6-4 is even better. to avoid solder wicking over to the via pads during soldering, it is important to have a solder mask of 4 mil around the pad (nsmd pad), this gives a di- ameter of 33 mil for a 25 mil ground pad. to obtain the optimum ground layout, place the vias directly under the ball pads. in this case no lo- cal boar d distortion is tolerated. the thickness of the copper on pcb layers is typ- ically 34 m m for external layers and 17 m m for inter- nal layers. this means thermal dissipation is not good and temperature of the board is concentrat- ed around the devices and falls quickly with in- creased distance. when it is possible to place a metal layer inside the pcb, this improves dramatically the heat spreading and hence thermal dissipation of the board. figure 6-2. recommended 1-wire ground pad layout figure 6-3. recommended 4-wire ground pad layout solder mask (4 mil) pad for ground ball (diameter = 25 mil) hole to ground layer (diameter = 12 mil) connection wire (width = 10 mil) via (diameter = 24 mil) 34.5 mil 1 mil = 0.0254 mm 4 via pads for each ground ball board layout issue 1.7 - february 8, 2000 43/48 the pbga package also dissipates heat through peripheral ground balls. when a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the peripheral ground balls. the more via pads are connected to each ground ball, the more heat is dissipated . the only limita- tion is the risk of lossing routing channels. figure 6-5 shows a routing with a good trade off between thermal dissipation and number of rout- ing channels. figure 6-4. optimum layout for central ground ball via to ground layer pad for ground ball clearance = 6mil diameter = 25 mil hole diameter = 14 mil solder mask diameter = 33 mil external diameter = 37 mil connections = 10 mil figure 6-5. global ground layout for good thermal dissipation ground pad via to ground layer board layout 44/48 issue 1.7 - february 8, 2000 a local ground plane on opposite side of the board as shown in figure 6-6 improves thermal dissipa- tion. it is used to connect decoupling capacitances but can also be used for connection to a heat sink or to the system's metal box for better dissipation. this possibility of using the whole system's box for thermal dissipation is very usefull in case of high temperature inside the system and low tempera- ture outside. in that case, both sides of the pbga should be thermally connected to the metal chas- sis in order to propagate the heat through the met- al. figure 6-7 illustrates such an implementation. figure 6-6. bottom side layout and decoupling ground plane for thermal dissipation via to ground layer figure 6-7. use of metal plate for thermal dissipation metal planes thermal conductor board die board layout issue 1.7 - february 8, 2000 45/48 6.2 high speed signals some interfaces of the stpc run at high speed and have to be carefully routed or even shielded. here is the list of these interfaces, in decreasing speed order: - memory interface. - graphics and video interfaces - pci bus - 14mhz oscillator stage all the clocks have to be routed first and shielded for speeds of 27mhz or more. the high speed sig- nals have the same contrainsts as some of the memory interface control signals. the next interfaces to be routed are memory, vid- eo/graphics, and pci. all the analog noise sensitive signals have to be routed in a separate area and hence can be rout- ed indepedently. figure 6-8. shielding signals ground ring ground pad shielded signal line ground pad shielded signal lines ordering data 46/48 issue 1.7 - february 8, 2000 7. ordering data 7.1 ordering codes st pc d01 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id d01: client core speed 66: 66mhz 75: 75mhz package bt: 388 overmoulded bga temperature range c: commercial case temperature (tcase) = 0 c to +100 c i: industrial case temperature (tcase) = -40 c to +100 c a: auatomotive case temperature (tcase) = -40 c to +115 c operating voltage 3 : 3.3v 0.3v ordering data issue 1.7 - february 8, 2000 47/48 7.2 available part numbers 7.3 customer service more information is available on the stmicroelectronics internet site http:// www.st.com/stpc. any specific questions are to be addressed direct- ly to the local st sales office. part number core frequency ( mhz ) cpu mode (dx/dx2) tcase range ( c) operating voltage (v) stpcd0166btc3 66 dx 0 c to +100 c 3.3v 0.3v stpcd0175btc3 75 dx stpcd0166bti3 66 dx -40 c to +100 c stpcd0175bti3 75 dx stpcd0166bta3 66 dx -40 c to +115 c information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 48 issue 1.7 |
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